The general construction of encapsulated semiconductor devices, for example ball grid array (“BGA”) packages, consists of a semiconductor chip mounted on an upper surface of a laminate substrate, both encased in a plastic resin encapsulant, and with a number of solder balls attached to the lower surface of the laminate substrate. The solder balls facilitate bonding the semiconductor package to a circuit card or board.
Traditionally, one of the most common BGA packages is a semiconductor chip that is electrically connected to electrical circuitry on a laminate substrate by conventional wire bonds or loop wire bonds. The semiconductor device has an over-molded plastic resin body that protects the semiconductor chip and the wire bonds, and this over-molded body may be up to 20 mils thick above the chip surface to adequately protect the wire loops. Consequently, the wire-bonded BGA has a relatively high thermal resistance for removing heat. As a result, the low heat dissipation capability makes the wire-bonded package unsuitable for high power applications.
Flip chip BGA's are a newer and thinner design that has better heat dissipation. Flip chip packages are semiconductor chips that have electrical connections in the form of solder bump contacts on the surface of the chip that faces (is adjacent to) the laminate substrate. Flip chip packages derive their name from the apparent flipping of the chip (with contacts down) so that the chip is upside down compared to that of the chip (with contacts up) in wire-bonded BGA's. Since the solder bumps are connected directly to the circuitry of the laminate substrate, there is no need for large wire loops or the thick molded plastic resin body that surrounds them.
A flip chip package typically requires an underfill material to keep moisture away from solder interconnections and to reinforce the solder joints that can be prone to fatigue. The underfill material surrounds the solder interconnections between the chip and the laminate substrate.
Flip chip packages have also been made with a thermally conductive covering, usually metal, to further improve heat transfer. The thermally conductive covering is attached to the chip with a thermal coupler or thermal interface material (“TIM”), such as an adhesive, a thermal paste, or a grease, to improve the transfer of heat from the chip to the thermally conductive covering. A flip chip package of this construction can have an additional problem since attachment of the thermally-conductive covering may result in delamination at the chip-to-covering interface. If the TIM is fairly rigid, the thermal coupler can fracture the chip. If the TIM is non-rigid, for example a thermal grease, it may displace during thermal cycling.
The current trend in high-end semiconductor device designs is to shrink the form factor (the dimensions and arrangement of the device) and to increase the integration level (the number of electronic circuits in the device). This means that the individual circuit components within an integrated circuit continually get smaller and smaller, while the integrated circuits themselves contain more and more circuits and circuit components. This leads to an increase in power density, and consequently worsens thermal management concerns.
Thermal management must therefore be addressed, both with regard to the design of the integrated circuit itself, and with regard to efficient thermal management at the packaging and at the system levels. Flip chip in package (“FCIP”) and flip chip-system in package (“FC-SiP”) configurations are widely used in such situations since they can be effectively tailored to provide significant thermal management. Unfortunately, the more successful prior FCIP and FC-SiP thermal management package designs have appeared in configurations that are manufactured in less-efficient singulated (rather than strip format) processes.
For reduced manufacturing costs, FCIP and FC-SiP configurations that are assembled in strip format are more favorable in many package size ranges. Unfortunately, current strip-format fabrication methods are unduly complicated and cumbersome, which defeats the potential efficiency and cost savings of strip-format manufacturing.
Thus, a need still remains for lower cost and less complicated semiconductor chip package designs and assembly processes, and particularly for package designs and assembly processes that are structured for efficient assembly in strip format. In view of the continuing increase in semiconductor device component and power densities, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.